1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and particularly to a standard cell used for design of a semiconductor integrated circuit.
2. Description of the Related Art
A standard cell method is one of the semiconductor integrated circuit design methods (layout techniques) of forming a highly integrated semiconductor integrated circuit on a semiconductor substrate. The standard cell method is a method for designing a desired large-scale integration (LSI) chip in the following manner: functional circuits as basic units constituting circuits such as an inverter and a NAND element are designed and verified in advance by humans or computer as standard cells; and a metal wiring layer is formed thereto. In a earlier standard cell method, a space for placement of a large transistor cannot be assured since standard cells are orderly arranged. However, when a large transistor is needed, a space for placement of the transistor is provided by extending a cell in the channel length direction of the transistor, or by placing cells continuously in the channel width direction.
A “double-height cell” is a cell where two cells are placed continuously in the channel width direction, and a large area for placement of a transistor can be thus provided either in a p-well region or in an n-well region. A “triple-height cell” is a cell where three cells are placed continuously in the channel width direction, and a large area can therefore be provided in both-p-well and n-well regions.
However, although a large area for placement of a transistor can be provided in a p-well region and/or an n-well region with respect to the earlier double-height and triple-height cells, there are also divided p-well and n-well regions above and below the large area. The space for placement of a transistor in the divided p-well and n-well regions is as small as that of an ordinary cell. Therefore, the possible size of the transistor to be placed in such an area is limited.